FRAMEFORM=RESERVED, FIELDFORM=ALL_SERIAL
SPIFI memory command register
| RESERVED | Reserved. |
| POLL | This bit should be written as 0. |
| DOUT | This bit should be written as 0. |
| INTLEN | This field controls how many intermediate bytes precede the data. (Each such byte may require 8 or 2 SCK cycles, depending on whether the intermediate field is in serial, 2-bit, or 4-bit format.) Intermediate bytes are output by the SPIFI, and include post-address control information, dummy and delay bytes. See the description of the Intermediate Data register for the contents of such bytes. |
| FIELDFORM | This field controls how the fields of the command are sent. 0 (ALL_SERIAL): All serial. All fields of the command are serial. 1 (QUADDUAL_DATA): Quad/dual data. Data field is quad/dual, other fields are serial. 2 (SERIAL_OPCODE): Serial opcode. Opcode field is serial. Other fields are quad/dual. 3 (ALL_QUADDUAL): All quad/dual. All fields of the command are in quad/dual format. |
| FRAMEFORM | This field controls the opcode and address fields. 0 (RESERVED): Reserved. 2 (OPCODE_ONE_BYTE): Opcode one byte. Opcode, least-significant byte of address. 3 (OPCODE_TWO_BYTES): Opcode two bytes. Opcode, 2 least-significant bytes of address. 4 (OPCODE_THREE_BYTES): Opcode three bytes. Opcode, 3 least-significant bytes of address. 5 (OPCODE_FOUR_BYTES): Opcode four bytes. Opcode, 4 bytes of address. 6 (NO_OPCODE_THREE_BYTE): No opcode three bytes. No opcode, 3 least-significant bytes of address. 7 (NO_OPCODE_FOUR_BYTES): No opcode, 4 bytes of address. |
| OPCODE | The opcode of the command (not used for some FRAMEFORM values). |